Peer Review History: Analytical Methods for Detecting and Eliminating the Static Hazard in Combinational Logic Circuits

Editor(s):

(1) Dr. Dariusz Jacek Jakóbczak, Koszalin University of Technology, Poland.

Approved by:

(1) Dr. Francisco Welington de Sousa Lima , Universidade Federal do Piauí, Teresina, Brazil.

Reviewers:

(1) Kosaraju Sivani, Kakatiya Institute of Technology & Science, India.

(2) P.Pattunnarajam, Anna University, India.

Additional Reviewers:

(1) Bwalya Moses, JAIN University, Zambia.

(2) Maryam Shaveisi, Kermanshah University of Technology, Iran.

(3) M  Mohammed Sabir Hussain, Muffakham Jah College of Engineering & Technology, Osmnia University, India.

(4) Sairoel Amertet Finecomes, Mizan Tepi University, Ethiopia.

(5) Sujatha Kotte, Osmania University, India.

(6) Uday kiran Elemasetty, University, Canada.

(7) Vasudeva Bevara, MREC(A), India.

Additional Reviewers: (Comments received after deadline)

Peer Review History:


Peer review report_1 (Kosaraju Sivani, India) | File 1 | NA


Peer review report_2 (P.Pattunnarajam, India) | File 1 | NA


Comment_Academic_Editor | File 1 | NA


Comment_Book_Editor | File 1 | NA


Posted in Review History.