Peer Review History: Design and Development of CPLD Based on Low Power Pipelined 64-bit RISC Processor with Unbiased Floating Point Unit

Editor(s):

(1) Prof. Rachid Masrour, Sidi Mohamed Ben Abdellah University, Morocco.

Reviewers:

(1) M Pradeep, Shri Vishnu Engineering College for Women (A), India.

(2) Yusuf Suryo Utomo, Indonesia.

Additional Reviewers:

Additional Reviewers: (Comments received after deadline)

Peer Review History:


Peer review report_1 (M Pradeep, India) | File 1 | NA


Peer review report_2 (Yusuf Suryo Utomo, Indonesia) | File 1 | File 2


Comment_Editor | File 1 | NA